- Information
- AI Chat
Final DEL Lab manual 2021-22 updated
Computer Engineering (310245D)
Savitribai Phule Pune University
Preview text
B. (2019 Pattern) Computer Engineering – Digital Electronics Lab
DEPARTMENT OF COMPUTER ENGINEERING
Savitribai Phule Pune University
Second Year of Computer Engineering (2019 Course)
Laboratory Manual
for
A. 2021-
210248 : Digital Electronics Laboratory
Companion Courses: 210245
Vision
Mission
#######
Program Education Objectives (PEOs)
Program Specific Outcomes (PSOs)
To create an Engineer, receptive to the changing demands of the global market.
To provide technically competent professionals in service to Nation.
To prepare graduates to respond to the needs of dynamically changing
technology.
PEO1: To prepare graduates to work productively as successful Computer
professionals.
PEO2: To prepare graduates with latest skills in the field of technologies
supplemented with practical orientation to face challenges of modern
computing industry.
PEO3: To provide environment that fosters professional growth,
communication skill, team work, life-long learning skill and ability to
create awareness in society about applications of technology.
PSO1 Problem Solving and Programming Skills: Graduates will be able to
apply computational techniques and complete individual practical experiences
in a variety of programming languages and situations.
PSO2 Professional Skills: Graduates will be able to design and develop
efficient and effective software by following standard software engineering
principles.
PSO3 Successful Career: Graduates will be able to become entrepreneur and
to pursue higher studies / career in IT industries.
####### `
Index
Sr.
No.
Title CO PO PSO
Page
No.
####### 1
Content To Bridge the Gap: To design and verify truth
table of Logic gates. C205 1,3 3
####### 2
To Realize Full Adder/ Subtractor using a) Basic Gates and
b) Universal Gates.
####### C205,
####### C205 1, 2, 3 1
####### 3
Design and implement Code Converters-Binary to Gray and
BCD to Excess-3.
####### C205,
####### C205.
####### 1, 2, 3 1
####### 4
Design and Realization of BCD Adder using 4-bit
Binary Adder (IC 7483).
####### C205,
####### C205.
####### 1, 2, 3 1
####### 5
Realization of Boolean Expression for suitable
combination logic using MUX 74151 /74153, DMUX
74154/74138.
####### C205,
####### C205 1, 2, 3 1
####### 6
To Verify the truth table of two bit comparators using
logic gates.
####### C205,
####### C205.
####### 1, 2, 3 1
####### 7
Design & Implement Parity Generator and checker using
EX-OR.
####### C205,
####### C205 1, 2, 3 1
####### 8
Design and Realization: Flip Flop conversion. C205,
####### C205.
####### 1, 2, 3 1,
####### 9
Design of 2 bit and 3 bit Ripple Counter using MS JK
flip-flop.
####### C205,
####### C205.
####### 1, 2, 3 1,
####### 10
Design of Synchronous 3 bit Up and Down Counter
using MSJK Flip Flop / D Flip Flop.
####### C205,
####### C205.
####### 1, 2, 3 1,
####### 11
Realization of Mod –N counter using (Decade Counter
IC 7490).
####### C205,
####### C205 1, 2, 3 1,
####### 12
Design and implement Sequence generator (for Prime
Number/odd and even) using MS JK flip-flop.
####### C205,
####### C205 1, 2, 3 1,
####### 13
Study of Shift Registers(SISO,SIPO,PISO,PIPO) C205,
####### C205,
####### C205.
####### 1,2,3,4 1,
####### 14
Beyond the Syllabus: Design and verify the 4-Bit Serial
in – Parallel out Shift Registers
####### C205,
####### C205 1,2,3 1,
Assignment No: 1
Title: Design and verify truth table of Logic gates.
Objective: To learn basic gates and verify its truth table.
Problem Statement : To Design and verify truth table of Logic Gates
i) AND
ii) OR iii) NOT iv) NAND v) NOR vi) EX-OR vii) EX-NOR
Hardware & software requirements: Digital Trainer Kit, IC 7404, IC 7432, IC 7408, IC 7486, IC 7400, IC 7402, Patch Cord, + 5V Power Supply
Theory:
i) AND Gate
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A dot
(.) is used to show the AND operation i. A or can be written as AB.
Y= A
ii) OR Gate
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.
A plus (+) is used to show the OR operation.
Y= A+B
vii) EX-NOR Gate
The 'Exclusive-NOR' gate circuit does the opposite to the EX-OR gate. It will give a low output if
either, but not both of its two inputs are high. The symbol is an EX-OR gate with a small circle on the
output. The small circle represents inversion.
Y= A ⊕ B
Conclusion:
Thus, we have studied logic gates and the truth tables have been verified using IC 7400, IC 7402, IC 7486, 7432, 7408, and 7404.
Question:
- Explain when output of AND is 1.
- Which gates can be used to implement EX-OR gate?
Assignment No: 2
Title: Design Full Adder/ Subtractor using a) Basic Gates and b) Universal Gates. Objective: To learn about adder, subtractor and its types. Problem Statement : To Realize Full Adder/ Subtractor using a) Basic Gates and b) Universal Gates.
Hardware & software requirements: Digital Trainer Kit, IC 7404, IC 7432, IC 7408, IC 7486, Patch Cord, + 5V Power Supply
Theory:
Adder: Adders are digital circuits that carry out addition of numbers. Adders are a key component of arithmetic logic unit. Types: 1. Half Adder 2. Full Adder
1. Half Adder: Half adder is a combinational circuit that performs simple addition of two binary numbers.
Sum = A B' + A' B Carry = AB
2. Full Adder: Full adder is a digital circuit used to calculate the sum of three binary bits. The additional third bit is carry bit from the previous stage and is called 'Carry' – in generally represented by CIN. It calculates the sum of three bits along with the carry.
Difference = A ⊕ B
Borrow = A' B
2. Full Subtractor: A full subtractor is a combinational circuit that performs subtraction involving three bits A (minuend), B (subtrahend) and a Bin (borrow bit) and it produces two outputs: D (difference) and Bout (borrow out).
D = A ⊕ B ⊕ Bin Bout = A' Bin + A' B + B Bin
Conclusion:
Thus, we have studied and implemented full adder/ subtractor using basic and universal gate.
Question:
- What is drawback of half adder/subtractor?
- What if full subtractor?
Binary to Gray Conversion
In this conversion, the input straight binary number can easily be converted to its Gray code equivalent.
- Record the most significant bit as it is.
- EX-OR this bit to the next position bit, record the resultant bit.
- Record successive EX-ORed bits until completed.
- Convert 0011 binary to Gray.
Gray to Binary Conversion
- The Gray code can be converted to binary by a reverse process.
- Record the most significant bit as it is.
- EX-OR binary MSB to the next bit of Gray code and record the resultant bit.
- Continue the process until the LSB is recorded.
- Convert 1011 Gray to Binary code.
1 0 1 1 Gray code
1 1 0 1 Binary code
(MSB) (LSB)
Fig. 2 Gray to Binary Conversion
3) BCD Code:
Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit binary code. For example (23) 10 is represented by 0010 0011 using BCD code rather than(10111) 2 This code is also known as 8- 4-2-1 code as 8421 indicates the binary weights of four bits(2 3 , 2 2 , 2 1 , 2 0 ). It is easy to convert between BCD code numbers and the familiar decimal numbers. It is the main advantage of this code. With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only 10 of these are used. The six code combinations (1010 to 1111) are not used and are invalid.
####### + +
0 0 1 1 Binary code
####### + + +
Fig. 1 Binary to Gray Conversion
Gray code
(MSB) (LSB)
0 0 1 0
####### +
Applications:
Some early computers processed BCD numbers. Arithmetic operations can be performed using this code. Input to a digital system may be in natural BCD and output may be 7-segment LEDs.
It is observed that more number of bits is required to code a decimal number using BCD code than using the straight binary code. However in spite of this disadvantage it is very convenient and useful code for input and
output operations in digital systems.
4) EXCESS-3 Code:
Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be used for the representation of multi-digit decimal numbers as can BCD code for each decimal number is obtained by adding decimal 3 and then converting it to a 4-bit binary number. For e. decimal 2 is coded as 0010
- 0011 = 0101 in Excess-3 code.
This is self complementing code which means 1‘s complement of the coded number yields 9‘s
complement of the number itself. Self complementing property of this helps considerably in
performing subtraction operation in digital systems, so this code is used for certain arithmetic
operations.
BCD To Excess – 3 Code Conversions:
Convert BCD 2 i. e. 0010 to Excess – 3 codes For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code using rules of
binary addition.
0010 + 0011 = 0101 – Excess – 3 code for BCD 2
Excess – 3 Code To BCD Conversion:
The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3 i. 0011 from 4 bit Excess-3 digit. e. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.
0101-0011= 0010- BCD for 2
3) Circuit Diagram:
Fig. 5 Logical Circuit Diagram for Binary to Gray Code Conversion
**B) Gray to Binary Code Conversion:
- Truth Table:**
Table 2 Gray to Binary Code Conversion INPUT (GRAY CODE) OUTPUT (BINARY CODE) G 3 G 2 G 1 G 0 B 3 B 2 B 1 B 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 1 0 0 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 0 0 1 1 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 1 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 1 1 1 1 1 0 1 0 1 1 1 0 1 0 1 1 1 0 1 0 1 1 0 0 1 0 1 1 1 1 0 1 1 0 0 1 1 1 1 0 1 0 0 0 1 1 1 1
2) K-Map for Reduced Boolean Expressions of Each Output:
Fig. 6 K-Map for Reduced Boolean Expressions of Each Output (Binary Code)
2) K-Map for Reduced Boolean Expressions of Each Output:
Fig. 8 K-Map for Reduced Boolean Expressions Of Each Output (Excess-3 Code)
3) Circuit Diagram:
Fig Logical Circuit Diagram for BCD to Excess-3 Code Conversion
**D) Excess-3 to BCD Conversion:
- Truth Table:**
Table 4 Excess-3 to BCD Conversion INPUT (EXCESS-3 CODE) OUTPUT (BCD CODE) E 3 E 2 E 1 E 0 B 3 B 2 B 1 B 0 0 0 0 0 X X X X 0 0 0 1 X X X X 0 0 1 0 X X X X 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 0 1 1 0 1 1 1 0 1 0 0 1 0 0 0 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 1 1 1 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 1 0 1 X X X X 1 1 1 0 X X X X 1 1 1 1 X X X X
2) K-Map for Reduced Boolean Expressions of Each Output:
Fig 10 K-Map For Reduced Boolean Expressions of Each Output (BCD Code)
Final DEL Lab manual 2021-22 updated
Course: Computer Engineering (310245D)
University: Savitribai Phule Pune University
This is a preview
Access to all documents
Get Unlimited Downloads
Improve your grades
