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Advanced Computer Architecture (18CS733)
Visvesvaraya Technological University
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Important :Note 1. On compleing your answers, compulsorily draw diagonal cross lincs o 2. Any revcaling of identification, appcal to cvaluator and lor cquations written cg, 42+8= 50, will be trcated as malpractíce. USN Time: 3 hrs. 1 2 3 4 6 b. a. b. c.
GBGS SGHEME
. Show the Flynn'sclassification ithe evolution of computerarchitectures. C. Explain static connection' networks in detail. a. Seventh Semester B. Degree Examináfion; JoreEfHuly 2023 Advanced Computer Architectures
####### a. Explain about program pactioning and grain packing,and scheduling.
b. Relate the Amdahl's and Gustafson's performancelaw. C. Note: AnSwer any FIVE full questions, choositgÖNE full question from each module.
####### Modile
llustrate detail about shared memorymåltiprocessors with neat diagram. Describe PRAM and VLSI models ith ncat diagram. OR
####### b. Differént-te the architectural ch¡racteristics of CISC and R processors.
C. Explànwith a diagram central árbiration and distributionárchitecture. Module- Sneerin OR i) TLB - Translation look aside Buffer LIBRARY JAYAUR Explain the architecture Qf VLI W processopand its pipeline operations. Explain the pros and cona of private virtual memory models in defail. Define the following terms: ii) Inclusion, coherence and loçality Qf reference. a. Explain the snooP system. Module- SA With a neat diagram, explain the RISC featíres of sun micro system SPARCarchitecture. Suminarize the linear andNonAinear pipelining models with a neat diagram. Deseribe the addressing-nd ~iming protocals in backplanc bus specification.
####### Demonstrate the instruçtioh pipelining tçehtqúes.
OR a. Describe the dËfferent types of yranslation models present in Bus system. Max, Marks: 100 b. Explain the twÑ cache addressing Hodels of cache memory organization. 18CS Module- lof (10 Marks) (05 Marks) (05 Marks) (10 Marks) (05 Marks) (05 Marks) (10 Marks) (05 Marks) (05 Marks) (10 Marks) (04 Marks) (06 Marks)
####### C. Jlustrate how shared memory ôrganization is achieving the memory consistency property.
(06 Marks) (06 Marks) (08 Marks) (04 Marks) (10 Marks) Bus protocol approach for cache coherence problem in multiprocessor (06 Marks) b. Show the archileduralcharacteristics of crosbar switch and multi port memory system. (10 Marks) (10 Marks)
10 8. hustrate the fotlowing terms associntcd with multi copyer net work i) Store and forward outing nt packet level i) Wormhle routing at lit level OR h Explain the vectot processing princ iple with compound vector processing. MOle- List and cxplain the various approaches 6fl Hiding techniques What is mcant by Branch prediction?) What arc thc different depcndenes, oNisting in Instruction Je v¢l'parallelism? VTU OR SA - SA - SA - SA - SA 2 of Demonstratc how thç-itedd levcl parallelism i_implemented to reduce thc limitations in cxploiting instruction level parallelism. Rclatc how the ópcfand forwarding and recorder buflering techniques in implementing instruction levelpgréllclism. nginue (10 Marks) LIBRARY) VIJAYAPUR 02-06-202301:35: 60 18CS SA - SA - SA - SA - SA - SA - SA - SA - SA (19 Marke) (06 Marlks) (06 Marks) (08 Marks) (10 Marks)
7 9 A i) What are the forbidden Iatencies? Write injtial dollision vector i) Dyaw the state tansition diagram a. i) List all simple cycles and grecdy cycles, b b iv) Detemine MAL. b. Explain the following with diag(am, With the help of diagram, cxplain Bàck Planc Bus Specification i) Dircct mapping ii) Fully associative cachc iii)Sct Associativc cathec. With the help ofdiagram, cxplain routing in orHega network. b. Explain different type of vector instructions with examples. c. Explain Snoopy bus protocol in detail. oR Differentiate betwccn low order memory interleaving and high order memory interleaving b. Explain the cache coherence problem with respe¢tto' i) Sharing of writable data Module ii) Process migration iii) /O activitý With the help ofdiagram, explain storc and forward outing and wormhole routing. C. Explain Directóry þased cache coherence,scheme. OR 10 aExplain Tomasulo's algorithm in detail. Explain compilation phases in paYallel code generation. i) Acto, Model Module- ii) Paralle lism of COOP Discuss the following in Object OrintedModel. i) Concurrent OOP
####### 2UAAPR
OR 18CS
jaoMara)
2 of (04Marks) (08 Marks) Mention 5 parallel programming models. Explain shared memory model in detatl (08 Marks) C Explain Register Renaming with example. (08 Marks) (04 Marks) (08 Marks) (08 Ma rks) (06 Marks) (06 Marks) (08 Marks) (03 Marks) (04 larks) (10 Marks) (10 Marks)
Important
Note:
1.
On
completing
your
answcompulsorily
draw
diagonal
cross
lines
on
the
remaininank
pages.
2.
Any
revealing
of
identification,
appeal
to
evaluator
and
/or
equations
written
eg,
42+8=
50,
will
be
treated
as
malpractíce.
USN
Time: 3 hrs.
1 2 3 4 5 6
a.
Note: Answer any FIVE full questions, cliousing ONE full questionTrom each module.
a. Explain the elements of modern topúter system with neat disgram.
a.
b.
Seventh Semester B. Degree Exa minatlon, July/August 2022
Advanced Computer
b. Describe with a neat diagram, different shared memory mutipYocessor models.
b.
c.
a.
S: ADD R2, R
S; : MOVE RI,Rs
S4 : Store B, Ry
(ii)
(iv)
GBGS SGHENE
Linear array
b. Explain he characteristics of the following static connection networks with diagram:
Define the types of data ependence. Also compute he dependence graph for the following
code segment
S:Load R, A
Binary tree
Module-
Chordal ring of degree 4
Mesh
(v) Torus
OR
Arçhitectures
Module
OR
Explain iF detail inclusion, çohetence and localitý properties.
Illustrate the four level memory hierarchy.
Define the various pago replacement policies.
connections.
SA- SA
18CST
Max. Marks: 100
Distinguish betwen RISCand CISC processor architectuês with block diagram. (10 Marks)
Explain VLIWprocessor architecture and its pipeline operations.
Module-
S
OR
(10 Marks)
(10 Marks)
(10Marks)
Iof 2
(10 Marks)
What is arbitratjon? Describe central arbitration and distributed arbitration with relevant
sketches.
(10 Marks)
(10 Marks)
(04 Marks)
b. Discuss physiça, address models and virtual address models for unified and split caches.
(06 Marks)
(10Marks)
a, Explain two-models oflingr pipeline units and the corresponding reservation table.
(10 Marks)
b. Explain the featsres Qf non-linear pipeline processor with feed forward and feed backward
(05 Marks)
(05 Marks)
On ImportantNote: appeal to evaluator and /or USN Time: 3 hrs. 2
####### Seventh Semester B. Degree Exanination, Feb./Mar. 2022
Advanced Conputer Architectures
b. C. Note: Answer any FIVE full questions, cho0sing ONE full question from each module. a. Explain Flyn's classification of computer architecture based on instruction stream and data stream. b. Explain in detail the types of shared memory multiprocessors. b
GBGS SCHEME
Instruction Type Integer Arithmetic Data Transfer Floating Point Control Transfer a) A 400 MHz processor was used to execute a bench mark program with the following instruction mix and clock cycle counts: Instruction count Clock Cycle Count 450000 320000 150000 a. Compare and contrast control flow and data flow architectures. Module-l 80000 Main memory Determine the effective CPI, MIPS, rate and execution time for the progranm. Sl:A=B+ D b) S2: C= A * S3: A =A+C S4: E= A/ Disk array |3 =4 ms OR Access Time t, =25 ns t, = unknown Perform adata dependence analysis on each of the following Fortran program fragments. Show the data dependency and resource dependency graphs among the statements. Sl:X= sin (X) S2:X + W What are the metrics affecting the scalability of a computer system? Explain. S3:Y = 2 *W S4: X = cos (2) Module- 2 Capacity S = 512 kb S, = 32 mb 18CS Max. Marks. 10 a. Apply the knowledge of memory hierarchy and explain the properties that every intomaion stored in a memory hierarchy should satisfy. S; = unknown Withthe knowledge of three level memory hierarchy, consider the foliowing specitications: Memory level Cache Cost/Kbyte Cj= 80. Iof C, S0. (06 Marks) C; =$0. (08 Marks) C. Compare and contrast the different instruction set architectures. (06 Marks) (08 Marks) (06 Marks) (06 Marks) (10Marks) The design goal is to achieve an eflective memory access time t = 850 ms with acache hit ratio h, = 0 and a hit ratio h2 = 0 in mnain memory. Calculate the memory access time t2 of the RAM to build main memory. Total cost of the memory hierarchy is Sl,500. Find S3. (04 Marks) (06 Marks) compieungyour answers, compulsonly draw diagonal cross lines on the remaining blank nages equations written eg. 42 +8-= 50. will be treated as malpractce
6 OR a. Branch out the schemes used for translating virtual address into physical address. (08 Marks) b. Make use of the following page trace 0 | 2 4 2372|3|Calculate the hit ratio for the following page replacement policies where page frarme 3. (i) FIFO (i) LRU (i) OFTIMAL C. Explain the coneept of virtual memory models with a neat diagram. () Dirrct mapping cache a. Compare the relative merits and demerits of the following cache memory orgarnization techniques: (iii) Set Associative cache (iv) Sector mapping cache () b. Consider the execution of aprogram of 15,000 instructions by a linear pipeline processor with a clock rate of 1000 MHz. Assume that the instruction pipeline has five stages and that one instruction is issued per clock cycle. The penalties due to branch instructions and out-of sequence exccutions are ignored. memory. (i) Calculate the speed-up factor in using this pipeline to execute the program as compared with the use of an equivalent non-pipelined processor with an equal of flow-through delay. amount (i) What are the efficiency and throughput ofthis pipelined processor? (06 Marks) Apply the knowledge of dynamic instruction scheduling and explain Tomosulo's algorithm with an example. (04 Marks) Module- S, X S a. Analyze and compare the ways to close-up the speed gap between CPU/cache and main X X X b. Consider the following reservation table for a three stage pipeline with a clock rate t 2ns. I 2 3 4 5 67 8 X X 18CS OR X (06 Marks) (06 Marks) X What are the forbidden latencies and the initial collision vector? (ü) Draw the state transition diagram for scheduling the pipeline. (üi) List all the simple cycles and greedy cycles. (iv) Determine the minimal average latency. (v) Determine the throughput of this pipeline. C. Explain any two bus arbitration techniques. (10 Marks) Module- 2 of (06 Marks) (10 Marks) (04 Marks) a. Design an Omega network and check whether the routing is permissible or blocked for the given permutation I = (0, 7, 6, 4, 2)(0, 3) (5) and 2 = (0, 6, 4, b. 7, 3) (1, 5) (2).
####### Apply the knowledge of cache coherence problems and
design a directory based protocol to (10 Marks) maintain data consistency. (10Marks) (ii) Fully associative cache
ACA question papers
Course: Advanced Computer Architecture (18CS733)
University: Visvesvaraya Technological University
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