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VLSI Design Module - 3 - Vtu notes of ece 7th sem vlsi 3rd mod 18th scheme
Electronic and communication (ECE)
Visvesvaraya Technological University
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Module - 3
Syllabus: Delay: Introduction, Transient Response, RC Delay Model, Linear Delay Model, Logical Efforts of Paths (4 to 4 of TEXT2, except sub-sections 4.3, 4.4, 4.4, 4.5 and 4.5). Combinational Circuit Design: Introduction, Circuit families (9 to 9 of TEXT2, except subsection 9.2).
Textbooks: 1. “CMOS Digital Integrated Circuits: Analysis and Design” - Sung Mo Kang & Yosuf Leblebici, Third Edition, Tata McGraw-Hill. 2. “CMOS VLSI Design- A Circuits and Systems Perspective”- Neil H. E. Weste and David Money Harris, 4th Edition, Pearson Education.
Delay
Definitions:
Propagation delay time, tpd: Maximum time from the input crossing 50% to the output crossing 50% Contamination delay time, tcd: Minimum time from the input crossing 50% to the output crossing 50% Rise time, tr: Time for a waveform to rise from 20% to 80% of its steady-state value Fall time, tf: Time for a waveform to fall from 80% to 20% of its steady-state value Edge rate,
Fig.3: Propagation delay and rise/fall times Rise/fall times are also sometimes called slopes or edge rates. Propagation and contamination delay times are also called max-time and min-time, respectively. The gate that charges or discharges a node is called the driver and the gates and wire being driven are called the load. Propagation delay is also called as delay. A timing analyzer computes the arrival times, i., the latest time at which each node in a block of logic will switch. The nodes are classified as inputs, outputs, and internal nodes. The user must specify the arrival time of inputs and the time data is required at the outputs. The arrival time ai at internal node i depends on the propagation delay of the gate driving i and the arrival times of the inputs to the gate. The timing analyzer computes the arrival times at each node and checks that the outputs arrive by their required time. The slack is the difference between the required and arrival times. Positive slack means that the circuit meets timing. Negative slack means that the circuit is not fast enough. Fig.3 shows nodes annotated with arrival times. If the outputs are all required at 200 ps, the circuit has 60ps of slack. A practical timing analyzer extends this arrival time model to account for a number of effects.
At the logic level Trade-offs include types of functional blocks (e., ripple carry vs. lookahead adders), the number of stages of gates in the clock cycle, and the fan-in and fan-out of the gates. The transformation from function to gates and registers can be done by experience, by experimentation, or, most often, by logic synthesis. At the circuit level the delay can be tuned by choosing transistor sizes or using other styles of CMOS logic.
The floorplan (either manually or automatically generated) is of great importance because
it determines the wire lengths that can dominate delay. Good cell layouts can also reduce
parasitic capacitance.
Transient Response:
The most fundamental way to compute delay is to develop a physical model of the circuit of interest, write a differential equation describing the output voltage as a function of input voltage and time, and solve the equation. The solution of the differential equation is called the transient response , and the delay is the time when the output reaches VDD/2. The differential equation is based on charging or discharging of the capacitances in the circuit. The circuit takes time to switch because the capacitance cannot change its voltage instantaneously. If capacitance C is charged with a current I, the voltage on the capacitor varies as:
Every real circuit has some capacitance. In an integrated circuit, it typically consists of the gate capacitance of the load along with the diffusion capacitance of the driver’s own transistors The transistor current depends on the input (gate) and output (source/drain) voltages. Fig.3 shows an inverter X1 driving another inverter X2 at the end of a wire. Suppose a voltage step from 0 to VDD is applied to node A and to compute the propagation delay, tpdf , through X1, (i., the delay from the input step until node B crosses VDD/2) requires the capacitance associated with each nodes.
Fig.3: Inverter driving an inverter load The capacitances associated are the diffusion capacitances between the drain and body Cdb of each transistor and between the source and body Csb of each transistor as shown in fig.3.
Fig.3: Capacitance for an inverter The gate capacitance Cgs of the transistors in X2 are part of the load. The wire capacitance is also part of the load. The gate capacitance of the transistors in X1 and the diffusion capacitance of the transistors in X2 do not matter because they do not connect to node B. The source-to-body capacitors Csbn1 and Csbp1 have both terminals tied to constant voltages and thus do not contribute to the switching capacitance. Therefore, the equivalent capacitances of inverter which are lumped into a single capacitance Cout is as shown in the fig.3.
An nMOS transistor of k times unit width has resistance R/k because it delivers k times as much current. A unit pMOS transistor has greater resistance, generally in the range of 2R–3R, because of its lower mobility. Gate and Diffusion Capacitance Each transistor also has gate and diffusion capacitance. We define C to be the gate capacitance of a unit transistor of either flavor. A transistor of k times unit width has capacitance kC. Diffusion capacitance depends on the size of the source/drain region. Equivalent RC Circuits Fig.3 shows equivalent RC circuit models for nMOS and pMOS transistors of width k with contacted diffusion on both source and drain.
Fig.3: Equivalent circuit for transistors The pMOS transistor has approximately twice the resistance of the nMOS transistor because holes have lower mobility than electrons.
The pMOS capacitors are shown with VDD as their second terminal because the n-well is connected to VDD. Fig.3 shows the equivalent circuit for a fanout-of-1 inverter with negligible wire capacitance. The inverters of fig.3(a) are composed from an nMOS transistor of unit size and a pMOS transistor of twice unit width to achieve equal rise and fall resistance.
Fig.3: Equivalent circuit for inverter Fig.3 (b) gives an equivalent circuit, showing the first inverter driving the second inverter’s gate. Fig.3(c) illustrates the equivalent circuit when input A rises, the nMOS transistor will be ON and the pMOS OFF. The capacitors shorted between two constant supplies are also removed because they are not charged or discharged. The total capacitance on the output Y is 6C. Equivalent circuit for 3-input NAND gate Fig.3 shows a 3-input NAND gate. To charge the output node any one pMOS transistor should be on. Therefore, the width of each pMOS transistor for a 3-input NAND gate must be equal to width of pMOS transistor in a symmetric inverter (for a symmetric inverter the width of pMOS transistor is 2 and width of nMOS transistor is 1).
Fig.3: Capacitance of each transistor in 3-input NAND gate Fig.3 shows the 3-input NAND gate with the equivalent capacitances lumped to ground. Each pMOS has input capacitance of 2C and each nMOS has input capacitance of 3C, therefore total input capacitance of 5C. Output capacitance of each nMOS transistor are 9C (each pMOS has 2C and nMOS has 3C), 3C and 3C.
Fig. 10 : Equivalent capacitance of each transistor in 3-input NAND gate Fig.3 shows the equivalent circuit for the falling output transition and rising output transition. The output pulls down through the three series nMOS transistors. In the worst case, the upper two inputs are 1 and the bottom one falls to 0. The output pulls up through a single
pMOS transistor. The upper two nMOS transistors are still on, so the diffusion capacitance between the series nMOS transistors must also be discharged.
Fig.3: Equivalent circuit for the falling and rising output transition
Elmore Delay:
In general, most circuits of interest can be represented as an RC tree, i., an RC circuit with no loops. The root of the tree is the voltage source and the leaves are the capacitors at the ends of the branches. The Elmore delay model estimates the delay from a source switching to one of the leaf nodes as the sum changing over each node i of the capacitance Ci on the node, multiplied by the effective resistance Ris on the shared path from the source to the node and the leaf. The Elmore delay is given by ∑
Consider the 2nd order RC system shown in the fig.3. The circuit has a source and two nodes.
Fig.3: Second order RC system
Therefore, the Elmore delay is tpd = (3w + 3m)C * (R/w) tpd = (3 + 3m/w)RC. The fanout of the gate, h, is defined as the ratio of the load capacitance to the input capacitance. The load capacitance is 3mC. The input capacitance is 3wC. Thus, the inverter has a fanout of h = m/w. Therefore, the delay can be written tpd = (3 + 3h)RC.
3. If a unit transistor has R = 10k and C = 0 in a 65nm process, compute the delay in picoseconds, of the inverter in shown in the figure with a fanout of h = 4.
The RC product in the 65 nm process is (10k) * (0) = 1 ps. For h = 4, the delay is (3 + 3h) * (1ps) = 15 ps.
4. Estimate tpdf and tpdr for the 3-input NAND gate if the output is loaded with h identical NAND gates. Consider the equivalent circuit for the falling transition as shown below. Each NAND gate load presents 5 units of capacitance on a given input.
Node n 1 has capacitance 3C and resistance of R/3 to ground. Node n 2 has capacitance 3C and resistance (R/3 + R/3) to ground. Node Y has capacitance (9 + 5h)*C and resistance (R/3 + R/3 + R/3) to ground. The Elmore delay for the falling output is the sum of these RC products, tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3 + R/3 + R/3) tpdf = (12 + 5h)RC. Consider the equivalent circuit for the rising transition as shown above. Each NAND gate load presents 5 units of capacitance on a given input. Node Y has capacitance (9 + 5h)C and resistance R to the VDD supply. Node n 2 has capacitance 3C. The relevant resistance is only R, not (R + R/3), because the output is being charged only through R. Similarly, node n 1 has capacitance 3C and resistance R. Hence, the Elmore delay for the rising output is tpdr = (15 + 5h)RC
Linear Delay Model:
The RC delay model showed that delay is a linear function of the fanout of a gate. Based on this observation, designers further simplify delay analysis by characterizing a gate by the slope and y-intercept of this function. In general, the normalized delay of a gate can be expressed in units of τ as d = f + p p is the parasitic delay inherent to the gate when no load is attached.
Fig.3 shows inverter, 3-input NAND, and 3-input NOR gates with transistor widths chosen to achieve unit resistance, assuming pMOS transistors have twice the resistance of nMOS transistors. The inverter has three units of input capacitance, so the logical effort is 1. The NAND has five units of capacitance on each input, so the logical effort is 5/3. The NOR has seven units of capacitance, so the logical effort is 7/3. Table 3 lists the logical effort of common gates. Table 3: Logical effort of common gates
The effort tends to increase with the number of inputs. NAND gates are better than NOR gates because the series transistors are nMOS rather than pMOS. Exclusive-OR gates are particularly costly and have different logical efforts for different inputs.
Parasitic Delay: The parasitic delay of a gate is the delay of the gate when it drives zero load. It can be estimated with RC delay models. A crude method good for hand calculations is to count only diffusion capacitance on the output node. For example, consider the gates in fig.3, assuming each transistor on the output node has its own drain diffusion contact. Transistor widths were chosen to give a resistance of R in each gate. The inverter has three units of diffusion capacitance on the output, so the parasitic delay τ is 3RC. In other words, the normalized parasitic delay is 1.
In general, the normalized parasitic delay is the ratio of diffusion capacitance to gate capacitance in a particular process. It is usually close to 1 and will be considered to be 1 in many examples for simplicity. The 3-input NAND and NOR each have 9 units of diffusion capacitance on the output, so the parasitic delay is three times as great (3pinv, or simply 3). Table 4 estimates the parasitic delay of common gates. Increasing transistor sizes reduces resistance but increases capacitance correspondingly Table 3: Parasitic delay of common gates
Logical Effort of Paths:
Delay in Multistage Logic Networks: Fig.3 shows the logical and electrical efforts of each stage in a multistage path as a function of the sizes of each stage. The path of interest (the only path in this case) is marked with the dashed blue line. Observe that logical effort is independent of size, while electrical effort depends on sizes.
Fig.3: Multistage Logic Networks The path logical effort G can be expressed as the products of the logical efforts of each stage along the path. ∏
capacitance without helping the pulldown current; hence, static CMOS has a relatively large logical effort. Many faster circuit families seek to drive only nMOS transistors with the inputs, thus reducing capacitance and logical effort. An alternative mechanism must be provided to pull the output high.
Circuit Families:
Static CMOS circuits with complementary nMOS pulldown and pMOS pullup networks are used for the vast majority of logic gates in integrated circuits. They have good noise margins, and are fast, low power, insensitive to device variations, easy to design, widely supported by CAD tools, and readily available in standard cell libraries. When noise does exceed the margins, the gate delay increases because of the glitch, but the gate eventually will settle to the correct answer. Most design teams now use static CMOS exclusively for combinational logic. Static CMOS:
Bubble Pushing: CMOS stages are inherently inverting, so AND and OR functions must be built from NAND and NOR gates. DeMorgan’s states that ̅̅̅̅ ̅ ̅ ̅̅̅̅̅̅̅̅ ̅ ̅ A NAND gate is equivalent to an OR of inverted inputs. A NOR gate is equivalent to an AND of inverted inputs.
Fig.3: Bubble pushing with DeMorgan’s law
The same relationship applies to gates with more inputs. Switching between these representations is often called bubble pushing. Design a circuit to compute F = AB + CD using NANDs and NORs. To design the circuit, it requires of two AND gates and an OR gate, as shown in fig.3(a). The ANDs and ORs are converted to basic CMOS stages as shown in fig.3(b). Bubble pushing is used to simplify the logic to NAND form stages as shown in fig.3(c and d).
Fig.3: Bubble pushing to convert ANDs and ORs to NANDs and NORs
Compound Gates: Static CMOS are used to implement compound gates for computing various inverting combinations of AND/OR functions in a single stage. The function F = AB + CD can be computed with an AND-OR-INVERT-22 (AOI22 – two-two-input AND gate) gate and an inverter, as shown in fig.3.
Fig.3: Complex Logic using AOI22 gate
VLSI Design Module - 3 - Vtu notes of ece 7th sem vlsi 3rd mod 18th scheme
Course: Electronic and communication (ECE)
University: Visvesvaraya Technological University
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