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RISC-V Refrence CARD - Green CARD

RISC -V green card
Course

Digital design (EC381)

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Academic year: 2023/2024
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Jack Daniel
جامعة طرابلس
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RISC-V Instruction Set Summary "Green Card"

Figure B RISC-V 32-bit instruction formats

Table B RV32I: RISC-V integer instructions

op funct3 funct7 Type Instruction Description Operation

0000011 (3) 000 – I lb rd, imm(rs1) load byte rd = SignExt([Address]7:0)

0000011 (3) 001 – I lh rd, imm(rs1) load half rd = SignExt([Address]15:0)

0000011 (3) 010 – I lw rd, imm(rs1) load word rd = [Address]31:

0000011 (3) 100 – I lbu rd, imm(rs1) load byte unsigned rd = ZeroExt([Address]7:0)

0000011 (3) 101 – I lhu rd, imm(rs1) load half unsigned rd = ZeroExt([Address]15:0)

0010011 (19) 000 – I addi rd, rs1, imm add immediate rd = rs1 + SignExt(imm)

0010011 (19) 001 0000000 * I slli rd, rs1, uimm shift left logical immediate rd = rs1 << uimm

0010011 (19) 010 – I slti rd, rs1, imm set less than immediate rd = (rs1 < SignExt(imm))

0010011 (19) 011 – I sltiu rd, rs1, imm set less than imm. unsigned rd = (rs1 < SignExt(imm))

0010011 (19) 100 – I xori rd, rs1, imm xor immediate rd = rs1 ^ SignExt(imm)

0010011 (19) 101 0000000 * I srli rd, rs1, uimm shift right logical immediate rd = rs1 >> uimm

0010011 (19) 101 0100000 * I srai rd, rs1, uimm shift right arithmetic imm. rd = rs1 >>> uimm

0010011 (19) 110 – I ori rd, rs1, imm or immediate rd = rs1 | SignExt(imm)

0010011 (19) 111 – I andi rd, rs1, imm and immediate rd = rs1 & SignExt(imm)

0010111 (23) – – U auipc rd, upimm add upper immediate to PC rd = {upimm, 12'b0} + PC

0100011 (35) 000 – S sb rs2, imm(rs1) store byte [Address]7:0 = rs27:

0100011 (35) 001 – S sh rs2, imm(rs1) store half [Address]15:0 = rs215:

0100011 (35) 010 – S sw rs2, imm(rs1) store word [Address]31:0 = rs

0110011 (51) 000 0000000 R add rd, rs1, rs2 add rd = rs1 + rs

0110011 (51) 000 0100000 R sub rd, rs1, rs2 sub rd = rs1 — rs

0110011 (51) 001 0000000 R sll rd, rs1, rs2 shift left logical rd = rs1 << rs24:

0110011 (51) 010 0000000 R slt rd, rs1, rs2 set less than rd = (rs1 < rs2)

0110011 (51) 011 0000000 R sltu rd, rs1, rs2 set less than unsigned rd = (rs1 < rs2)

0110011 (51) 100 0000000 R xor rd, rs1, rs2 xor rd = rs1 ^ rs

0110011 (51) 101 0000000 R srl rd, rs1, rs2 shift right logical rd = rs1 >> rs24:

0110011 (51) 101 0100000 R sra rd, rs1, rs2 shift right arithmetic rd = rs1 >>> rs24:

0110011 (51) 110 0000000 R or rd, rs1, rs2 or rd = rs1 | rs

0110011 (51) 111 0000000 R and rd, rs1, rs2 and rd = rs1 & rs

0110111 (55) – – U lui rd, upimm load upper immediate rd = {upimm, 12’b0}

1100011 (99) 000 – B beq rs1, rs2, label branch if = if (rs1 == rs2) PC = BTA

1100011 (99) 001 – B bne rs1, rs2, label branch if ≠ if (rs1 ≠ rs2) PC = BTA

1100011 (99) 100 – B blt rs1, rs2, label branch if < if (rs1 < rs2) PC = BTA

1100011 (99) 101 – B bge rs1, rs2, label branch if ≥ if (rs1 ≥ rs2) PC = BTA

1100011 (99) 110 – B bltu rs1, rs2, label branch if < unsigned if (rs1 < rs2) PC = BTA

1100011 (99) 111 – B bgeu rs1, rs2, label branch if ≥ unsigned if (rs1 ≥ rs2) PC = BTA

1100111 (103) 000 – I jalr rd, rs1, imm jump and link register PC = rs1 + SignExt(imm), rd = PC + 4

1101111 (111) – – J jal rd, label jump and link PC = JTA, rd = PC + 4

• imm: signed immediate in imm11:

• uimm: 5-bit unsigned immediate in imm4:

• upimm: 20 upper bits of a 32-bit immediate, in imm31:

• Address: memory address: rs1 + SignExt(imm11:0)

• [Address]: data at memory location Address

• BTA: branch target address: PC + SignExt({imm12:1, 1'b0})

• JTA: jump target address: PC + SignExt({imm20:1, 1'b0})

• label: text indicating instruction address

• SignExt: value sign-extended to 32 bits

• ZeroExt: value zero-extended to 32 bits

• csr: control and status register

*encoded in instr31:25, the upper seven bits of the immediate field

Table B RV64I: Extra integer instructions

op funct3 funct7 Type Instruction Description Operation

0000011 (3) 011 – I ld rd, imm(rs1) load double word rd = [Address]63:

0000011 (3) 110 – I lwu rd, imm(rs1) load word unsigned rd = ZeroExt([Address]31:0)

0011011 (27) 000 – I addiw rd, rs1, imm add immediate word rd = SignExt((rs1 + SignExt(imm))31:0)

0011011 (27) 001 0000000 I slliw rd, rs1, uimm shift left logical immediate word rd = SignExt((rs131:0 << uimm)31:0)

0011011 (27) 101 0000000 I srliw rd, rs1, uimm shift right logical immediate word rd = SignExt((rs131:0 >> uimm)31:0)

0011011 (27) 101 0100000 I sraiw rd, rs1, uimm shift right arith. immediate word rd = SignExt((rs131:0 >>> uimm)31:0)

0100011 (35) 011 – S sd rs2, imm(rs1) store double word [Address]63:0 = rs

0111011 (59) 000 0000000 R addw rd, rs1, rs2 add word rd = SignExt((rs1 + rs2)31:0)

0111011 (59) 000 0100000 R subw rd, rs1, rs2 subtract word rd = SignExt((rs1 — rs2)31:0)

0111011 (59) 001 0000000 R sllw rd, rs1, rs2 shift left logical word rd = SignExt((rs131:0 << rs24:0)31:0)

0111011 (59) 101 0000000 R srlw rd, rs1, rs2 shift right logical word rd = SignExt((rs131:0 >> rs24:0)31:0)

0111011 (59) 101 0100000 R sraw rd, rs1, rs2 shift right arithmetic word rd = SignExt((rs131:0 >>> rs24:0)31:0)

Table B RVF/D: RISC-V single- and double-precision floating-point instructions

op funct3 funct7 rs2 Type Instruction Description Operation

1000011 (67) rm fs3, fmt – R4 fmadd fd,fs1,fs2,fs3 multiply-add fd = fs1 * fs2 + fs

1000111 (71) rm fs3, fmt – R4 fmsub fd,fs1,fs2,fs3 multiply-subtract fd = fs1 * fs2 — fs

1001011 (75) rm fs3, fmt – R4 fnmsub fd,fs1,fs2,fs3 negate multiply-add fd = —(fs1 * fs2 + fs3)

1001111 (79) rm fs3, fmt – R4 fnmadd fd,fs1,fs2,fs3 negate multiply-subtract fd = —(fs1 * fs2 – fs3)

1010011 (83) rm 00000, fmt – R fadd fd,fs1,fs2 add fd = fs1 + fs

1010011 (83) rm 00001, fmt – R fsub fd,fs1,fs2 subtract fd = fs1 — fs

1010011 (83) rm 00010, fmt – R fmul fd,fs1,fs2 multiply fd = fs1 * fs

1010011 (83) rm 00011, fmt – R fdiv fd,fs1,fs2 divide fd = fs1 / fs

1010011 (83) rm 01011, fmt 00000 R fsqrt fd,fs1 square root fd = sqrt(fs1)

1010011 (83) 000 00100, fmt – R fsgnj fd,fs1,fs2 sign injection fd = fs1, sign = sign(fs2)

1010011 (83) 001 00100, fmt – R fsgnjn fd,fs1,fs2 negate sign injection fd = fs1, sign = —sign(fs2)

1010011 (83) 010 00100, fmt – R fsgnjx fd,fs1,fs2 xor sign injection fd = fs1,

sign = sign(fs2) ^ sign(fs1)

1010011 (83) 000 00101, fmt – R fmin fd,fs1,fs2 min fd = min(fs1, fs2)

1010011 (83) 001 00101, fmt – R fmax fd,fs1,fs2 max fd = max(fs1, fs2)

1010011 (83) 010 10100, fmt – R feq rd,fs1,fs2 compare = rd = (fs1 == fs2)

1010011 (83) 001 10100, fmt – R flt rd,fs1,fs2 compare < rd = (fs1 < fs2)

1010011 (83) 000 10100, fmt – R fle rd,fs1,fs2 compare ≤ rd = (fs1 ≤ fs2)

1010011 (83) 001 11100, fmt 00000 R fclass rd,fs1 classify rd = classification of fs

RVF only

0000111 (7) 010 – – I flw fd, imm(rs1) load float fd = [Address]31:

0100111 (39) 010 – – S fsw fs2,imm(rs1) store float [Address]31:0 = fd

1010011 (83) rm 1100000 00000 R fcvt.w rd, fs1 convert to integer rd = integer(fs1)

1010011 (83) rm 1100000 00001 R fcvt.wu rd, fs1 convert to unsigned integer rd = unsigned(fs1)

1010011 (83) rm 1101000 00000 R fcvt.s fd, rs1 convert int to float fd = float(rs1)

1010011 (83) rm 1101000 00001 R fcvt.s fd, rs1 convert unsigned to float fd = float(rs1)

1010011 (83) 000 1110000 00000 R fmv.x rd, fs1 move to integer register rd = fs

1010011 (83) 000 1111000 00000 R fmv.w fd, rs1 move to f. register fd = rs

RVD only

0000111 (7) 011 – – I fld fd, imm(rs1) load double fd = [Address]63:

0100111 (39) 011 – – S fsd fs2,imm(rs1) store double [Address]63:0 = fd

1010011 (83) rm 1100001 00000 R fcvt.w rd, fs1 convert to integer rd = integer(fs1)

1010011 (83) rm 1100001 00001 R fcvt.wu rd, fs1 convert to unsigned integer rd = unsigned(fs1)

1010011 (83) rm 1101001 00000 R fcvt.d fd, rs1 convert int to double fd = double(rs1)

1010011 (83) rm 1101001 00001 R fcvt.d fd, rs1 convert unsigned to double fd = double(rs1)

1010011 (83) rm 0100000 00001 R fcvt.s fd, fs1 convert double to float fd = float(fs1)

1010011 (83) rm 0100001 00000 R fcvt.d fd, fs1 convert float to double fd = double(fs1)

fs1, fs2, fs3, fd: floating-point registers. fs1, fs2, and fd are encoded in fields rs1, rs2, and rd; only R4-type also encodes fs3. fmt: precision of computational

instruction (single=00 2 , double=01 2 , quad=11 2 ). rm: rounding mode (0=to nearest, 1=toward zero, 2=down, 3=up, 4=to nearest (max magnitude), 7=dynamic).

sign(fs1): the sign of fs1.

In RV64I, registers are 64 bits, but instructions are still 32 bits. The term “word” generally refers to a 32-bit value. In RV64I, immediate shift instructions use

6-bit immediates: uimm5:0; but for word shifts, the most significant bit of the shift amount (uimm 5 ) must be 0. Instructions ending in “w” (for “word”) operate

on the lower half of the 64-bit registers. Sign- or zero-extension produces a 64-bit result.

Table B RISC-V pseudoinstructions

Pseudoinstruction RISC-V Instructions Description Operation

nop addi x0, x0, 0 no operation

li rd, imm11:0 addi rd, x0, imm11:0 load 12-bit immediate rd = SignExtend(imm11:0)

li rd, imm31:0 lui rd, imm31:12 *

addi rd, rd, imm11:

load 32-bit immediate rd = imm31:

mv rd, rs1 addi rd, rs1, 0 move (also called “register copy”) rd = rs

not rd, rs1 xori rd, rs1, —1 one’s complement rd = ~rs

neg rd, rs1 sub rd, x0, rs1 two’s complement rd = —rs

seqz rd, rs1 sltiu rd, rs1, 1 set if = 0 rd = (rs1 == 0)

snez rd, rs1 sltu rd, x0, rs1 set if ≠ 0 rd = (rs1 ≠ 0)

sltz rd, rs1 slt rd, rs1, x0 set if < 0 rd = (rs1 < 0)

sgtz rd, rs1 slt rd, x0, rs1 set if > 0 rd = (rs1 > 0)

beqz rs1, label beq rs1, x0, label branch if = 0 if (rs1 == 0) PC = label

bnez rs1, label bne rs1, x0, label branch if ≠ 0 if (rs1 ≠ 0) PC = label

blez rs1, label bge x0, rs1, label branch if ≤ 0 if (rs1 ≤ 0) PC = label

bgez rs1, label bge rs1, x0, label branch if ≥ 0 if (rs1 ≥ 0) PC = label

bltz rs1, label blt rs1, x0, label branch if < 0 if (rs1 < 0) PC = label

bgtz rs1, label blt x0, rs1, label branch if > 0 if (rs1 > 0) PC = label

ble rs1, rs2, label bge rs2, rs1, label branch if ≤ if (rs1 ≤ rs2) PC = label

bgt rs1, rs2, label blt rs2, rs1, label branch if > if (rs1 > rs2) PC = label

bleu rs1, rs2, label bgeu rs2, rs1, label branch if ≤ (unsigned) if (rs1 ≤ rs2) PC = label

bgtu rs1, rs2, label bltu rs2, rs1, offset branch if > (unsigned) if (rs1 > rs2) PC = label

j label jal x0, label jump PC = label

jal label jal ra, label jump and link PC = label, ra = PC + 4

jr rs1 jalr x0, rs1, 0 jump register PC = rs

jalr rs1 jalr ra, rs1, 0 jump and link register PC = rs1, ra = PC + 4

ret jalr x0, ra, 0 return from function PC = ra

call label jal ra, label call nearby function PC = label, ra = PC + 4

call label auipc ra, offset31:12 *

jalr ra, ra, offset11:

call far away function PC = PC + offset, ra = PC + 4

la rd, symbol auipc rd, symbol31:12 *

addi rd, rd, symbol11:

load address of global variable rd = PC + symbol

l{b|h|w} rd, symbol auipc rd, symbol31:12 *

l{b|h|w} rd, symbol11:0(rd)

load global variable rd = [PC + symbol]

s{b|h|w} rs2, symbol, rs1 auipc rs1, symbol31:12 *

s{b|h|w} rs2, symbol11:0(rs1)

store global variable [PC + symbol] = rs

csrr rd, csr csrrs rd, csr, x0 read CSR rd = csr

csrw csr, rs1 csrrw x0, csr, rs1 write CSR csr = rs

op funct3 Type Instruction Description Operation

1110011 (115) 000 I ecall transfer control to OS (imm=0)

1110011 (115) 000 I ebreak transfer control to debugger (imm=1)

1110011 (115) 000 I uret return from user exception (rs1=0,rd=0,imm=2) PC = uepc

1110011 (115) 000 I sret return from supervisor exception (rs1=0,rd=0,imm=258) PC = sepc

1110011 (115) 000 I mret return from machine exception (rs1=0,rd=0,imm=770) PC = mepc

1110011 (115) 001 I csrrw rd,csr,rs1 CSR read/write (imm=CSR number) rd = csr,csr = rs

1110011 (115) 010 I csrrs rd,csr,rs1 CSR read/set (imm=CSR number) rd = csr,csr = csr | rs

1110011 (115) 011 I csrrc rd,csr,rs1 CSR read/clear (imm=CSR number) rd = csr,csr = csr & ~rs

1110011 (115) 101 I csrrwi rd,csr,uimm CSR read/write immediate (imm=CSR number) rd = csr,csr = ZeroExt(uimm)

1110011 (115) 110 I csrrsi rd,csr,uimm CSR read/set immediate (imm=CSR number) rd = csr,

csr = csr | ZeroExt(uimm)

1110011 (115) 111 I csrrci rd,csr,uimm CSR read/clear immediate (imm=CSR number) rd = csr,

csr = csr & ~ZeroExt(uimm)

Table B Privileged / CSR instructions

* If bit 11 of the immediate / offset / symbol is 1, the upper immediate is incremented by 1. symbol and offset are the 32-bit PC-relative addresses of a label

and a global variable, respectively.

For privileged / CSR instructions, the 5-bit unsigned immediate, uimm, is encoded in the rs1 field.

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RISC-V Refrence CARD - Green CARD

Course: Digital design (EC381)

8 Documents
Students shared 8 documents in this course

University: جامعة طرابلس

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RISC-V Instruction Set Summary "Green Card"
Figure B.1 RISC-V 32-bit instruction formats
Table B.1 RV32I: RISC-V integer instructions
op funct3 funct7 Type Instruction Description Operation
0000011 (3) 000 –Ilb rd, imm(rs1) load byte rd = SignExt([Address]7:0)
0000011 (3) 001 –Ilh rd, imm(rs1) load half rd = SignExt([Address]15:0)
0000011 (3) 010 –Ilw rd, imm(rs1) load word rd = [Address]31:0
0000011 (3) 100 –Ilbu rd, imm(rs1) load byte unsigned rd = ZeroExt([Address]7:0)
0000011 (3) 101 –Ilhu rd, imm(rs1) load half unsigned rd = ZeroExt([Address]15:0)
0010011 (19) 000 –Iaddi rd, rs1, imm add immediate rd = rs1 + SignExt(imm)
0010011 (19) 001 0000000*Islli rd, rs1, uimm shift left logical immediate rd = rs1 << uimm
0010011 (19) 010 –Islti rd, rs1, imm set less than immediate rd = (rs1 < SignExt(imm))
0010011 (19) 011 –Isltiu rd, rs1, imm set less than imm. unsigned rd = (rs1 < SignExt(imm))
0010011 (19) 100 –Ixori rd, rs1, imm xor immediate rd = rs1 ^ SignExt(imm)
0010011 (19) 101 0000000*Isrli rd, rs1, uimm shift right logical immediate rd = rs1 >> uimm
0010011 (19) 101 0100000*Israi rd, rs1, uimm shift right arithmetic imm. rd = rs1 >>> uimm
0010011 (19) 110 –Iori rd, rs1, imm or immediate rd = rs1 | SignExt(imm)
0010011 (19) 111 –Iandi rd, rs1, imm and immediate rd = rs1 & SignExt(imm)
0010111 (23) – – Uauipc rd, upimm add upper immediate to PC rd = {upimm, 12'b0} + PC
0100011 (35) 000 –Ssb rs2, imm(rs1) store byte [Address]7:0 = rs27:0
0100011 (35) 001 –Ssh rs2, imm(rs1) store half [Address]15:0 = rs215:0
0100011 (35) 010 –Ssw rs2, imm(rs1) store word [Address]31:0 = rs2
0110011 (51) 000 0000000 R add rd, rs1, rs2 add rd = rs1 + rs2
0110011 (51) 000 0100000 R sub rd, rs1, rs2 sub rd = rs1 — rs2
0110011 (51) 001 0000000 R sll rd, rs1, rs2 shift left logical rd = rs1 << rs24:0
0110011 (51) 010 0000000 R slt rd, rs1, rs2 set less than rd = (rs1 < rs2)
0110011 (51) 011 0000000 R sltu rd, rs1, rs2 set less than unsigned rd = (rs1 < rs2)
0110011 (51) 100 0000000 R xor rd, rs1, rs2 xor rd = rs1 ^ rs2
0110011 (51) 101 0000000 R srl rd, rs1, rs2 shift right logical rd = rs1 >> rs24:0
0110011 (51) 101 0100000 R sra rd, rs1, rs2 shift right arithmetic rd = rs1 >>> rs24:0
0110011 (51) 110 0000000 R or rd, rs1, rs2 or rd = rs1 | rs2
0110011 (51) 111 0000000 R and rd, rs1, rs2 and rd = rs1 & rs2
0110111 (55) – – Ului rd, upimm load upper immediate rd = {upimm, 12’b0}
1100011 (99) 000 –Bbeq rs1, rs2, label branch if = if (rs1 == rs2) PC = BTA
1100011 (99) 001 –Bbne rs1, rs2, label branch if ≠ if (rs1 ≠ rs2) PC = BTA
1100011 (99) 100 –Bblt rs1, rs2, label branch if < if (rs1 < rs2) PC = BTA
1100011 (99) 101 –Bbge rs1, rs2, label branch if ≥ if (rs1 ≥ rs2) PC = BTA
1100011 (99) 110 –Bbltu rs1, rs2, label branch if < unsigned if (rs1 < rs2) PC = BTA
1100011 (99) 111 –Bbgeu rs1, rs2, label branch if ≥ unsigned if (rs1 ≥ rs2) PC = BTA
1100111 (103) 000 –Ijalr rd, rs1, imm jump and link register PC = rs1 + SignExt(imm), rd = PC + 4
1101111 (111) – – Jjal rd, label jump and link PC = JTA, rd = PC + 4
• imm: signed immediate in imm11:0
• uimm: 5-bit unsigned immediate in imm4:0
• upimm: 20 upper bits of a 32-bit immediate, in imm31:12
• Address: memory address: rs1 + SignExt(imm11:0)
• [Address]: data at memory location Address
• BTA: branch target address: PC + SignExt({imm12:1, 1'b0})
• JTA: jump target address: PC + SignExt({imm20:1, 1'b0})
• label: text indicating instruction address
• SignExt: value sign-extended to 32 bits
• ZeroExt: value zero-extended to 32 bits
• csr: control and status register
*encoded in instr31:25, the upper seven bits of the immediate field

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